资源列表
123
- 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
sdcard.tar
- 最新的基于wishbone总线的sd卡控制器设计-Latest sd card controller design based on the wishbone bus
truck_lights
- Lights, Car light emulator for turn, stop and emergency
ADC_16bit
- 16位ADC的verilog源代码 16-bit Analogue-Digital Converter-16-bit ADC verilog source code 16-bit Analogue-Digital Converter
mux42
- 一个四选一多路选择器 ，元件例化生成八个元件，八个结果相与输出结果-A four-elect more than one-way selector component instantiation generates eight components, the eight results of phase output
jishuqi
- verilog计数器，很实用，很经典，实际测试过的，免费下载吧，-verilog counter, very practical, very classic, the actual test, Free!
VHDL-control-Lantern
- 用VHDL实现彩灯的控制，使彩灯以不同的方式显示出来，且可以正确运行。-Lantern control using VHDL lanterns displayed in different ways, and can be run properly.
123
- 一个汉字显示源程序，关于用VHDL,大家可以参考一下-A Chinese character display source code using VHDL, we can refer to
12
- 用VHDL变得一段用于1602lcd显示的程序，大家可以参考一下-VHDL has become for some procedures for 1602lcd display, we can refer to
lfsr
- the LFSR is coded in VHDL, using a structural descr iption, which is instantiated as a separate component in the top-level design. Then we can get a random number by a pseudorandom number generator based on a linear feedback shift register (LFS
Sum_of_2_rand
- We produce two 5-bit random numbers and then adds them. The two random numbers are generated by pressing two different push-buttons on the lab board. The addition is controlled by a third button, button3. it can be implemented on the Atlys board.
Mulitiplier_Hardwired_Control
- The code is a multiplier that use the structure of datapath and hardwired control. It can be implemented on the Atlys board.