资源列表
SAYEH
- Verilog 数字系统设计---综合、测试平台与验证 .书中源程序-cpu in verilog descr iption. include C language source
fpga_msp430
- fpga和msp430进行通信，包括他们之间的通信协议-Fpga and msp430 in communication，Including the communication protocol between them
jishuqi
- 在fpga实验版上实现4位7段数码管动态显示，数字递增-In fpga experimental edition to realize four 7 period of digital tube dynamic display, digital increasing
fpga_test
- 此程序用来测试fpga和msp430单片机通信是否正确-This procedure used to test fpga and msp430 single chip microcomputer communication is correct
autoseller
- autoseller machine is the main function of the code with the language of verilog. it is accomplished with the state machine.
FIFO
- FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input
LED-VARIETY
- 实现四盏灯的流水显示，适合初学者学习，电路简单，通俗易懂-Water to achieve the four lights display, suitable for beginners to learn the circuit is simple, easy to understand
led
- 控制8个发光二极管中的一个发光二极管发光，其它7个发光二极管都出于截止状态，发光二极管的导通顺序按照向左或向右两个方向移动，并且通过按键控制发光二极管循环发光移动的方向。-Control of a light-emitting diode light-emitting eight light-emitting diodes, the other seven light-emitting diodes for the cut-off state, light-emitting diode cond
full_adder
- 全加法器，全加器描述，由两个半加器连接而成-full adder
rs232
- 通过串口通信来控制8位led灯的显示，可以通过串口调试工具来发送信号控制LED灯的亮灭-UART Serial communication control led lights display
lab7
- bcd seven segment decoder in vhdl on spartan 3e board
Homework4
- 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis