资源列表
uartrx
- FPGA的verilog uart 接收端程序。非常实用-The FPGA verilog uart receiving end procedures. Very practical
DE2_115_Default
- ALTERA DE2 115开发板实用例程，默认程序，大量引脚定义，很有参考价值-ALTERA DE2 115 development board utility routines, the default program, a large pin definitions, useful reference
Karasimsek
- A VHDL implementation of Karasimsek
SHA1
- SHA1 implementation on FPGA VHDL code
Sha3_candidate
- Sha3 candidate implementation on FPGA
Behavioral-Groestl
- GROESTL hash algoritm implementation on FPGA
Thesis_SHA
- Document based on SHA implementation architecture
VHDL-design-technique
- 可编程逻辑器件(plc)VHDL设计教程-Programmable logic devices (plc) VHDL Design Tutorial
FPGAReference-to-study
- FPGA参考学习资料， EDA技术的应用与开发-FPGA reference learning materials, EDA technology application and development
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
daba
- 采用verilog 语言编写的打靶程序，配合黑金四代开发板，可以VGA屏幕上显示闪烁打点。打点坐标可以自我设置，也可以由外设用给。-Using verilog language targeting program, with four generations of black gold development board, VGA screen flashes RBI. RBI coordinates can be self-set can also be used by the periphe
clk_div
- 任意频率脉冲可调，同时占空比为定值50 -Arbitrary frequency pulse adjustable, while 50 of the duty cycle is constant