资源列表
fifo_env
- for synchronization when we are dealing with 2 different clock domain
huxi
- 基于VHDL设计四个频率不同的呼吸灯，呼吸频率分别为 0.1Hz,0.2Hz，0.4Hz，0.8Hz 呼吸灯原理：利用PWM波控制led的亮度，的 原始代码 quartus软件亲测可用。-VHDL-based design in four different frequencies breathing light, breathing frequency was 0.1Hz, 0.2Hz, 0.4Hz, 0.8Hz breathing light principle: the use PWM
daojishi
- 基于VHDL编写的60S倒计时，可以设置倒计时开始时间， 重置倒计时，倒计时结束数码管会闪烁，蜂鸣器报警，quartus软件亲测可用。-60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
zuoye60
- 基于VHDL的60S倒计时设计，附带数码管显示，倒计时完成后蜂鸣器报警-60S countdown VHDL-based design, with a digital display, the countdown is completed after the buzzer alarm
verilog
- 《verilog_数字系统设计课程》(第二版)思考题答案-" Verilog_ Digital System Design Course" (Second Edition) Questions answers. Rar
Video-and-Image-Processing-Suite
- 视频图像处理方法介绍altera公司相关文章-Video image processing method described in
behavioral
- 8:3 encoder using behavioral modeling
dataflow
- 4:2 encoder using data flow modeling
structural
- 4:2 ENCODER USING STRUCTURAL MODELING
CameraLink_Oserdes2_test
- 40M时钟输入经过iserdes倍频到960M-input 40M o clock and output 960M
CLK_TEST
- VHDL实现的8分频程序，经测试，在板上运行成功-8 divided clock
VGA_256
- 基于FPGA的VGA驱动，能在显示器上实现256色-FPGA-based VGA driver to achieve 256 colors on the display