资源列表
INS_Reg_Dec---Copy
- Instruction REgister
CISC-Processor-MOdule-Verilog
- Cisc Processor For Se-Cisc Processor For Sell
Loadshedding
- This is a project using FPGA for implementing the preferential loadshedding schemes.
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
FREQUENCY_COUNTER_DISPLY_BLOCK
- 四位数字频率计 Four digital frequency meter- Four digital frequency meter
aurora_1_example
- serial communication using aurora core
ex2_key
- VHDL-按键消抖实验程序,采用EMP240处理器，希望对大家有用-VHDL-key debounce experimental procedures used EMP240 processor, we hope to be useful
switch_power_identify
- FPGA实现智能数控电压，此为FPGA代码，器件为A3PN250,软件为libro。采集电压电流参数，实现PID调节，通过串口通信配置，实现输出电压和保护点的调节。- ON划词翻译ON实时翻译 FPGA intelligent digital voltage, this FPGA code, based on A3PN250, the software for the libro. Acquisition of vo
PCM30-Verilog-source-code
- 使用Verilog设计PCM30基群帧同步电路 电路功能说明： 1．输入码流DATA，速率为2.04Mb/S；每帧256bit，其中前8bit为帧同步码；偶数帧的帧同步码为10011011，奇数帧的帧同步码为110XXXXX（X为任意值）。 2．系统初始状态为失步态，失步信号FLOSS输出低电平，电路在输入码流里逐比特搜寻同步码，当搜寻到第一个偶帧同步码后，电路转为逐帧搜寻，当连续三帧均正确地搜寻到同步码后，系统状态转为同步态，失步信号输出高电平；否则电路重新进入逐比特搜寻状态。
dvi_ctrl_ch7301c
- controller of CH7301C DVI Transmitter Device
spi
- SPI controller-SPI controller
vga_gen
- VGA Timing generator-VGA Timing generator