资源列表
clock_end
- 基于Quartus II 9.0 的电子时钟，用VHDL语言编写，显示时钟，星期等，可以调整。-Quartus II 9.0-based electronic clock, using VHDL language, display clock, week, etc., can be adjusted.
pid
- 基于FPGA的PID控制器的设计 VHDL源码-Design of PID controller based on FPGA VHDL source code
set_abl_clk_i
- this a set_able_clock. like some in auto mobile.-this is a set_able_clock. like some in auto mobile.
a_multipl_b
- this a multipelier that multiple 2 number in 8 bit.-this is a multipelier that multiple 2 number in 8 bit.
a_sum_b
- this is a 2 bit adder for xilinx with ise 9.2
divideer_2
- this is a 2 bit divider for xilinx whit ise 9.2
ram_4_4
- this is a 2 bit ram for xilinx whit ise 9.2
kechengsheji
- 拨码开关控制点阵显示十进制数 内含VHDL PDF等文件-DIP switches control the dot matrix display contains a decimal number, such as VHDL PDF file
myvhdl
- 用VHDL实现了简单的程序编写和仿真。是一个10进制计数器。-Using VHDL to make a simple 10 counter and it s simulation
D_A_CONTROLER
- AD5546芯片的控制逻辑，只需送入待转换量，该模块即可完成对芯片的写入等功能。-AD5546 chip control logic, simply amount to be converted into the chip module to complete the write functions.
disp
- 数码管扫描程序，只需送入32BIT的数据，该模块即可控制八位数码管得到相应的显示。-Digital scanner, simply fed 32BIT data, the module can control eight corresponding digital display.
uC_CISC_16_Design
- Verilog Based CISC Processor.....Availble for Purchase...rahulshandilya@outlook.com