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- Java.curriculum.FileWatch.module.code Java课程设计FileWatch模块代码Java curriculum design FileWatch module code
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- InvertedPendulum this code is for control of an inverted pendulum using state space representation
- (ebook-pdf)-Verilog-Language verilog 语言学习文档
资源列表
wcdma.v
- 无线通信FPGA设计例13-6源代码，WCDMA系统小区搜索的FPGA实现 -Example 13-6 FPGA design of wireless communication source code, FPGA implementation of WCDMA system cell search
dtrig
- 用vhdl实现的设计D触发器的程序，主要用在时序电路中。-Using vhdl implementation procedures for the design of D flip-flop, mainly used in sequential circuits.
cmosmt9m001_model
- 该verilog程序是型号为mt9m001的cmos图像传感器的仿真模型，能够输出频率为30Hz不同分辨率的图像。-This code is the simulation model of mt9m001 cmos sensor,it can output 30Hz and different resolution figure.
15x15mul
- 自己写的布斯4算法的华莱士树无符号数乘法器，3-2压缩，亲测可用-Wallace wrote the number 4 Booth algorithm unsigned multiplier, 3-2 compression, pro-test available
sramceshi
- 用VERILOG编写的测试SRAM代码，已通过板级测试，完整无误-SRAM with the VERILOG code written test, have passed the board-level test, complete and correct
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
temcon
- 此程序用汇编语言写的，适用于51系列的单片机，程序有详细的注解。-this procedure was used assembly language and applicable to the Series 51 microcontroller, the procedures detailed footnotes.
LCD
- 基于vhdl语言的LCD控制程序代码及仿真
FPGA-logic-design-considerations
- FPGA逻辑设计注意事项， 这是一个在逻辑设计中注意事项列表，由此引起的错误常使得设计不可靠或速度较慢，为了提高设计性能和提高速度的可靠性，必须确定设计通过所有的这些检查。-FPGA logic design considerations, this is a note in the list of logical design, which often makes the design errors caused by unreliable or slow, in order to impro
dsp-builder-7.2-crack
- 5款altera的FPGA开发板原理图，详细介绍了板子的构成及功能-Altera paragraph 5 of the FPGA development board schematics, detailed information on the composition and functions of board
Falcon_E25GT_Plugin
- 用于xilinx FPGA芯片的DSP功能的一些例子，在世闻开发板E25GT上验证通过。-DSP chips for xilinx FPGA features some of the examples on earth smell development board E25GT verified.
altera_avalon_sdram_slave
- Altera avalon sdram controller salve.