资源列表
mdio_slave_interface
- Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Media Access Controller (MAC)
and_gate
- And gate testbench, testbench to simulate and run in modelsim
ADCaPLL
- 在FPGA上编写的通过SPI总线配置外部PLL芯片AD9518和ADC9268的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external PLL chip AD9518 and ADC9268 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the
pci_gr
- vhdl code for Simple PCI target interface
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
VHDL程序范例
- 这是有关VHDL的一些范例，可以通过范例学习一点东西，巩固自己学过的东西-This is the VHDL some examples, examples can learn something consolidate learned things
dianti.vhd
- 电梯控制器的VHDL源程序 很有代表性 经简单修改后可用于n层控制 -Lift Controller
dma_0
- SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
verilog111
- verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦-verilog things properly used it, it is an essential learners verilog things oh
costas_loop
- 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
stop_watch
- stopwatch source it is maded by maxplus2
VHDL Digital Clock
- A digital stop watch designed in VHDL