资源列表
S4_LCD_V
- 基于FPGA处理器EP1C6024008的1602Verilog源程序.-FPGA-based processor EP1C6024008 the 1602Verilog source.
mips
- 利用Verilog HDL硬件描述语言实现单周期MIPS_CPU设计。-Design of single-cycle MIPS_CPU
loadGIF
- 使用sdk读取GIF文件 需要相应的vgsdk库来运行项目-use sdk read GIF files need vgsdk corresponding to the operation of the project
edalock
- 4位电子密码多设计具有清除密码，重置密码，上锁密码和修改密码等功能。-Four electronic combination lock design, have modification password, clear the password reset the password, locking the password etc. Function.
MIMA
- 本程序是一个密码锁程序。包括四位密码的读取、识别、设置等。-This program is a combination lock program. Including four password to read, identification, setting, etc.
vcpwmcpldcar
- vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码
DEMO_45_RAM
- 这是描述一个ram的vhdl语言，很经典的哦-This is the descr iption of a ram in vhdl language it beautiful
BlazeNoC_QoS-master
- BlazeNoC_QoS：支持QoS的可重配置片上网络路由，有很高的性能。此代码包括完整的Xilinx ISE的工程，可以很方便地修改和移植。-BlazeNoC_QoS: QoS-reconfigurable chip network routing, a high performance. This code includes a complete Xilinx ISE project, can be easily modified and transplantation.
ADI_FPGA8_RevA_ise10migration
- xinlinx ADI开发板lvds传输-xinlinx ADI development board lvds transmission
checksum_master_onchip2.7z
- 学习sopc builder当中自定制元件的最经典最全面的例子，绝对超值-Learning sopc builder customized component among the most classic examples of the most comprehensive, the absolute value
nova_latest.tar
- VERILOG source code of a H.264 baseline decoder.
5354
- 图像的中值滤波算法及其FPGA实现Image median filtering algorithm and its FPGA implementation-Image median filtering algorithm and its FPGA implementation