资源列表
DDS
- 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
mustafaokanyolcakar
- divide-and-conquer algorithm for finding the position of the largest element in an array
lab7
- bcd seven segment decoder in vhdl on spartan 3e board
spi
- spi控制器，可以自己修改成8/16/32位模式-SPI controller
PWM_moto_ctrl
- verilog 代码实现 直流电机PWM控制 内有整个完整工程 和modelsim仿真文件-verilog code for PWM DC motor control to achieve within the whole integrity of engineering and modelsim simulation files
pa3_libguide_ug
- actel开发环境libero中应用到是一些基础宏的说明文档，很难得的资料-libero in actel application development environment are the basis of the documentation of the macro, it is difficult to get information
MyVGA_BouncingBall
- VHDL code for bouncing ball throw VGA port
shuzishizong
- 通过按键实现数字时钟的时间调节和 闹钟调节 -Digital clock alarm clock is adjustable
FPGA-experiment
- fpga经验总结，fpga系统设计的主要思路和方法初探-the fpga Experience fpga design ideas and methods of the
Cymometer
- 这是本人用verilog语言做的频率计！对于硬件来说是很好的程序.-This is my language to do with verlog frequency counter!
E7_3
- 对基于符号LMS算法的自适应均衡器进行仿真。要求分别进行算法的性能仿真、生成FPGA测试用的输入信号、仿真权值在运算过程中的数据范围(The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the da
FPGA-TOOL-chipscope
- FPGA的仿真工具chipscope pro的使用方法-FPGA simulation tools to use chipscope pro