资源列表
2channel-selector
- EPM1270 VHDL 2路选择器。完整文件夹包-EPM1270 VHDL 2 way selector. Complete document wallets
D-trigger
- FPGA EPM1270 VHDL D触发器。完整文件夹包-FPGA EPM1270 VHDL D flip-flop. Complete document wallets
3_8-decoder
- CPLD EPM1270 VHDL 3-8译码器。-CPLD EPM1270 VHDL 3-8 decoder.
sw2reg
- 利用Nexys3板子完成的实验Lab15:开关数据加载到寄存器并显示的设计与实现。适合用Nexys3的FPGA初学者参考。-Experimental use Nexys3 complete board Lab15: switch data is loaded into the register and display design and implementation. Suitable Nexys3 of the FPGA reference for beginners.
lcd_control
- 基于FPGA控制LCD液晶显示学号的veilog代码-FPGA-based LCD display student number controls the veilog code
VHDL
- 基于VHDL语言和CPLD开发板的，分频电路电路的开发。-Based on VHDL and CPLD development board, divider circuit circuit development.
51_FPGA
- 51单片机与FPGA之间通讯，FPGA扩展出通讯端口-51 communication between the MCU and FPGA, FPGA expansion of the communication port
FPGA-based-PWM-generator
- 基于FPGA的PWM发生器，将所需的正弦波和三角波转化为数据文件，存入存储器中，用计数器逐一读取产生波形-FPGA-based PWM generator, the desired sine wave and triangular wave into a data file into memory, and one by one to read the counter generates a waveform
uart
- 用verilog写的程序实现串口通信， 用verilog写的程序实现串口通信， -the program is based on verilog, and it s fuction is comunicate with uart
smartWasher
- QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作-QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action
pinlvji
- (FPGA Verilog)测量频率、周期、脉冲宽度 -(FPGA Verilog) measuring the frequency, period, pulse width
digital-clock
- Project of digital clock made in vhdl code.