资源列表
Verilogexample
- VERILOG实例，是学习verilog的好资料-Verilog instance, is to learn good information on Verilog
LatticeMico8_v3_1_VHDL
- LATTICE 公司的开放的8位CPU核.-Open 8bit cpu IP from Lattice.
spi_m
- 使用verilog硬件描述语言编写的SPI接口程序，通过仿真验证。-Using verilog hardware descr iption language prepared by the SPI interface program, verified by simulation.
ledseg
- 这是一个数码管的ip核，只需将想要显示的值写进对应的apb寄存器就可在对应的数码管上显示-This is a digital tube of IP core, you only need to want to show the value of the written into the corresponding apb register can be displayed on the corresponding digital tube
dingshiqi2
- 我的课程作业，59:59定时器，板子晶振50mHZ-My coursework, 59:59 timer board crystal 50mHZ
TrafficLights
- It is often useful to be able to sequence through an arbitrary number of states, staying in each state an arbitrary amount of time. For example, consider the set of traffic lights shown in Figure 8.13. The lights are assumed to be at a four
Verilog
- verilog编程语言的讲解，有电子科技大学出版-verilog programming language to explain, there is the University of Electronic Science and Technology Publishing
Quartus2-Verilog
- 对quartus2软件讲解，并且基于quartus2的verilog相关的程序编写-Explanation of quartus2 software, and the quartus2 based Verilog related programming
16b_bcd20
- 十六位的二进制转为二十位的BCD码，传给大家供大家分享-Sixteen twenty binary into BCD code, passed to everyone for sharing
uart_verilog
- Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
verilog-HDL-code
- Verilog HDL程序设计实例详解的源代码-verilog HDL code
SHUZIZHONG
- VHDL语言编写的数字钟程序，在quartus软件下编写。-VHDL language digital clock program, prepared in quartus software.