资源列表
clk_DCM_50to75MHz
- 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency mult
GV8500_Data_Sheet
- HD-SDI线驱芯片的资料，讲述SDI工作原理，对SDI初学都很有帮助！-HD-SDI cable driver chip information about SDI working principle of SDI are very helpful for beginners!
zobrazenie_16_bit_cisla_paralel
- 16 bit switch input view in hexa format on 7seg display
FPGA_BasicProgram
- 本人收集大部分FPGA的基础参考例程，包括各种接口技术如I2C,RS232,UART,SPI，PS/2等，还有驱动各种LCD如1602，NOKIA5110,FPGA超声波测距，FPGA控制ADS7825,ADS7844,ADS2807,THS1206,TLC2543,TLC5510A,MAX1312等，FPGA控制舵机，步进电机，niosii。-I collected most of the FPGA-based reference routines, including a variety o
master_i2c
- 主I2C程序，完成LED读写,寄存器读写-master_i2c verilog
testbench_learn
- 自己写的一个移位寄存器的实例，该例子主要用来讲述verilog中的testbench的写作，以及在testbench中怎样使用task，以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to m
AD7470con
- 该代码实现了AD转换芯片AD7470的控制，且已经通过试验验证，请放心使用-The code implements the AD converter chip AD7470 control, and has been verified by experiment, ease of use! ! !
fengpingqi
- 分频器，输入50MHz,可输出10KHZ，1KHZ，100Hz,10Hz,1Hz.-Divider, input 50MHz, can output 10KHZ, 1KHZ, 100Hz, 10Hz, 1Hz.
PCI-MINI
- pci 32位33M的从设备接口的实现源代码，使用verilog语言设计的，对设计自己的pci软核很有参考价值。-pci 32 位 33M slave device interface source code, using verilog language design, the design of their pci soft core of great reference value.
pip_example_design_3c120_vdk_v80
- altera vip,具体参考an427文档！-altera vip, specific reference an427 documentation!
fpga
- 新手报到，贡献一些FPGA设计的电子书，希望对大家有用。-Novice report, contribute some FPGA design books, I hope useful.
VHDL
- These are some vhdl program-These are some vhdl program...