资源列表
4weiquanjiaqi
- 4位全加器由3个模块构成。首先，通过实例引用基本门级元件xor、and定义底层的半加器模块halfadder，接着实例引用两个半加器模块halfadder和一个基本或门元件or组合成为全加器模块fulladder，最后实例引用4个1位的全加器模块fulladder构成4位全加器的顶层模块-4 full adder by the three modules. First, the basic gate-level component instance references xor, and def
shuzihongdianlu
- 数字钟电路的实现，可以24小时计时，可调整时间！-Digital clock circuit implementation, a 24-hour timer, adjustable time!
qicehweideng
- 汽车尾灯控制电路的设计，正常行驶时，6个尾灯全灭，刹车时，尾灯按一定频率闪烁，左转时，左侧灯轮流闪烁，右转时，右侧的灯轮流闪烁。-Control circuit design taillights, normal driving, six taillights Quanmie, brake, tail lights flashing at a certain frequency, turn left, turn left flashing lights, turn right, the righ
PHA
- Verilog编写的两路信号的相位测量相关内容，可计算两路信号的相位差，及当前频率-Verilog prepared by the two-way signal phase measurements related content, calculate the phase difference between two signals, and the current frequency
Latch
- 閂鎖器在FPGA的代表 使用verilog HDL-Latch on behalf of the FPGA using verilog HDL
FREQMODN
- 描述在verilog中除頻電路的verilog代碼-Described in verilog verilog code divider circuit
Digital-frequency-meter
- 用VHDL完成12位十进制数字频率计的设计及仿真-Using VHDL completed 12 decimal digits frequency of the design and simulation
DigitalOscilloscope
- verlog 编写的基于xilinx 的xc2s400 的数字示波器代码。-verlog prepared based on the xilinx xc2s400 digital oscilloscope code.
FPGA--TRAFFIC-LIGHT-LIN
- FPGA的VHDL程序课程设计。智能交通灯，可以使四路有效灯实现交叉交通警报提示。-FPGA VHDL program curriculum design. Intelligent traffic lights, you can make four lights to achieve effective cross-traffic alert notification.
UART-FPGA
- verilog的UART通信，解决了接受过程中的毛刺问题，将接受和发送两个过程独立开来-The UART verilog communication, solve problems receiving glitches during the process of receiving and sending two separate open
modelsim
- modelsim的初学教程，quartus10以上的版本不自带时序仿真，modelsim仿真好用-modelsim beginner tutorials, quartus10 above version does not own timing simulation, modelsim simulation handy
smg_8
- 基于verilog HDL预言的8段数码管驱动程序，模块化-Predictions based on verilog HDL 8 digital tube driver, modular