资源列表
frequency-phase_test_vhdl
- 相位差测试，频率测试、频率计数器、闸门控制器、显示译码控制的vhdl程序
DE2_115_pin_assignments
- de2-115引脚的配置，quartusII的设置-de2-115 configuration pins, quartusII settings
bujindianjiVHDL
- 步进电机定位控制系统VHDL程序与仿真波形．已经在xilinx ISE 8.1上验证．完全正确．-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
VHDLbell
- 采用VHDL语言设计了一个打铃系统。该系统已经调试，可适当参考。-Using VHDL language designed a system to fight bell. The system has been debugging, can be an appropriate reference.
11122604338152
- 用FPGA驱动LCD显示的VHDL程序，URAT VHDL程序与仿真-Driven LCD display with FPGA VHDL program
shuzizhong
- 基于vhdl的具备闹钟提醒的多功能数字钟设计与应用-The alarm clock to remind vhdl-based multi-functional digital clock design and application
chap11
- 《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
LCD-control-procedures
- 使用VHDL语言，编写的LCD控制VHDL程序与仿真-Using VHDL language, prepared by the LCD control procedures and VHDL simulation
p_s
- 用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
RAMFIFO_Ctrl_LFSR
- RAMFIFO with LFSR Controller
04301090a-u-law
- mod 16 counter using vhdl