资源列表
fir_gen
- finite impulse response generator verilog code
high_speed_tap8_DDS
- 用verilog编写的高速8路并行dds模块，用于与高速da(1ghz或以上)接口产生任意频率正弦波，模块已经经过工程验证，用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the prod
ellipf
- 经过精心设计的滤波器的代码，并在FPGA硬件平台实现和验证过的
i2c
- its a source code for i2c
taxi_top
- 编写的出租车计费器程序，包括原文件和仿真文件等，注释详细-Taxi meter written procedures, including the original files and simulation files, detailed notes
ad7304
- a program for AD-Wandler ad7304 in VHDL-Language
ocs-dpsk
- 利用目前最顶级光通信仿真软件VPI平台，此程序可以仿真实现在光载射频系统中的抑制载波差分相移调制（OCS-DPSK）调制格式-Optical communications using the most top VPI simulation software platform, this program can be simulated to achieve the optical carrier suppressed-carrier RF systems in the differential
whb4to1QDVHDL1
- whb4选1抢答器VHDL设计1,比较简单实用，我得课程设计初稿
AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
trafficlights
- 用VHDL语言实现是状态机的交通信号灯的程序源代码，用三种方式实现。-Using VHDL language is a state machine source code of traffic lights, in three ways.
simulation
- SDRAM控制器，ALTEAR公司的IP原核的testbech,很难得-SDRAM controller, ALTEAR' s IP pronuclei testbech, hard to come by
rs2
- 我自己做的rs 编解码，里面有全套的程序，已经运行通过，可以放心使用-I do rs codec, which has a full range of program has been run through, you can rest assured that use