资源列表
clkdiv
- Verilog UART分频时钟 产生9600波特率-Verilog UART baud rate divided clock generated 9600
uart_tx
- UART 发送端程序 verilog语言编写 9600波特率-UART transmit side program verilog language 9600 baud
uartrx
- FPGA的verilog uart 接收端程序。非常实用-The FPGA verilog uart receiving end procedures. Very practical
DE2_115_Default
- ALTERA DE2 115开发板实用例程，默认程序，大量引脚定义，很有参考价值-ALTERA DE2 115 development board utility routines, the default program, a large pin definitions, useful reference
Karasimsek
- A VHDL implementation of Karasimsek
SHA1
- SHA1 implementation on FPGA VHDL code
Sha3_candidate
- Sha3 candidate implementation on FPGA
Behavioral-Groestl
- GROESTL hash algoritm implementation on FPGA
Thesis_SHA
- Document based on SHA implementation architecture
VHDL-design-technique
- 可编程逻辑器件(plc)VHDL设计教程-Programmable logic devices (plc) VHDL Design Tutorial
FPGAReference-to-study
- FPGA参考学习资料， EDA技术的应用与开发-FPGA reference learning materials, EDA technology application and development
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE