资源列表
06.Anvyl_vga_Demo
- 用VHDL写的VGA程序，使用与xilinx开发板。-Written using VHDL VGA procedures, using xilinx development board.
03.Anvyl_KYPD_SEG_Demo
- 用VHDL写的KEY程序，使用与xilinx开发板。-KEY program written using VHDL, use and xilinx development board.
clock
- 基于VHDL的数字时钟设计，能很好的模拟数字时钟显示-VHDL-based digital clock design, can be a good analog and digital clock display
frequence1
- 基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。-FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.
seven_persons
- 自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。-Seven people to write their own voting machine verilog program to achieve four or more people pass through function.
barrel_shifter
- 自己写的环形移位寄存器的verilog程序，功能是由输入控制左移的位数，实现循环左移。-Write your own ring shift register verilog procedures, functions are controlled by the input number of digits left to achieve the left circle.
encoder104
- 独热码到二进制代码的转换即10输入4输出的二进制编码器的verilog程序。-One-hot code to binary code conversion, or 10 inputs 4 outputs the binary encoder verilog program.
enhanced_seven_seg
- 具有使能端的7段译码器，低电平有效，使能为高时有效，实现二进制代码到7段译码器的编码，使能为低时输出全部为1.-Enable end with 7-segment decoder, active low, Enable is active high and achieve binary code to seven segment decoder encoding output enable is low as a whole.
mux4_with_en
- 带有使能端的4输入数据选择器，S0, S1, S2, C0, C1为输入，C1，C2为使能输入，P, Q, R, T为输出，c1c2=00时输出全为0，c1c2=01时输出全为1，c1c2=10时数据选择，c1c2=11时输出是c1c2=10时的反。-4 with Enable input data selector, S0, S1, S2, C0, C1 as input, C1, C2 an enable input, P, Q, R, T as an output, c1c2 = 00 a
src
- 基于Xilinx FPGA的数字频率计，包括测频测周期测脉宽测占空比等-Xilinx FPGA-based digital frequency meter, including frequency measurement measuring duty cycle pulse testing, etc.
Cont_THS1207
- FPGA控制THS1207多通道ADC的verilog源代码-FPGA control THS1207 multi-channel ADC' s verilog source code
1bit-shumaguan-display
- EPM1270 VHDL 1位数码管动态显示。完整文件夹包-EPM1270 VHDL 1-bit digital tube dynamic display. Complete document wallets