资源列表
LCD1602
- 通过编写verilog语言完成数据的在液晶LCD1602显示-By writing verilog language to complete the data displayed on the LCD LCD1602
KEYS
- 在ISE环境下按键子程序完成多个独立按键的控制-The ISE environment keys subroutines multiple independent control keys
ADC0809
- ADC0809的verilog实现 及仿真的文件 和仿真的波形图-ADC0809 implementation and simulation of verilog files and simulation waveforms
LED8x8
- 8x8点阵的verilog实现，包含仿真testbench，和仿真的波形图-8x8 dot matrix verilog achieve, including simulation testbench, and simulation waveforms
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
prng
- 采用线性同余法的素数模乘同余发生器产生随机数,采用5级流水线设计-Using a linear congruential method prime modulus multiplicative congruential random number generator, using five pipeline design
adc_ads7842
- 由system verilog编写的adc_ads7842的驱动模拟程序-Adc_ads7842 verilog prepared by the driving simulator
shumaguan
- verilog 写的，基于CPLD 的数码管实验，输入端是430单片机，cpld做了38译码器和8位所存-verilog written CPLD-based digital tube experiments, the input is 430 single, cpld made 38 decoder and 8 kept
VHDL_ReversibleCounter
- 可逆计数器(两位十六进制,以十进制方式显示即从00,01数到14,15然后00,01再到根据10hz晶振(低频都可选,视板子情况而定)作为时间脉冲计数,rst键可以重置(清零 )计数器,drct键选择加法计数还是减法计数.-2-bit-Hexadecimal Reversible Counter(decimal display)
Alarm_Microblaze_ASM
- A Alarm system writed in Assembly to use on a Microblaze VHDL project.
dds_again
- 基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。-FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.