资源列表
MyFrequencyDesign
- 基于单片机msp430和cpld的高精度频率计。测频范围为0至20MHz。误差在万分之一。可以测量0至100KHz周期，脉宽。-Msp430 microcontroller-based and cpld precision frequency meter. Frequency measurement range of 0 to 20MHz. Error in a million. Can measure 0 to 100KHz cycle, pulse width.
rng
- wishbone规格下的rng代码的实现，自己编写顶层模块可以在modelsim下实现仿真-wishbone rng specifications under the implementation of the code, you can write your own top-level module under modelsim for simulation
ltc1068
- ltc1068简易数控滤波器（1k-20kHz）verilog-ltc1068 Simple NC filter (1k-20kHz) verilog
Xilinx-stacked-silicon-interconnect-technology.zi
- Xilinx stacked silicon interconnect technology Xilinx stacked silicon interconnect technology
SmartFusion2-Data-sheet-
- SmartFusion2 Data sheet SmartFusion2 Data sheet -SmartFusion2 Data sheet SmartFusion2 Data sheet SmartFusion2 Data sheet
3333333
- 基于vhdl语言的同步fifo的宏模块调用程序，可学习fpga的宏模块调用方法-Synchronous fifo vhdl language-based macro block the calling program, can learn fpga macro module calls methods
FPGA
- 分频器是FPGA设计中使用频率非常高的基本设计之一,该文详细介绍了任意数分频的设计方法-Divider FPGA design is a very high frequency of use is one of the basic design, the paper details the design of any number of methods divide
FPGAstudy
- verilog books .it is worth reading
usb_fifo_ft245b
- 基于FT245BM的FIFO接口设计 根据usb blaster改动-FT245BM FIFO interface design based on the changes under the usb blaster
Bus_Enable
- veilog小程序 参考设计中的 该程序说明了如何使用一个总线-veilog applet reference design of the program shows how to use a bus
BlackJack
- 本人利用FPGA实现的二十一点游戏程序，其中顶层电路用sch文件给出，每个模块使用VHDL语言编写-I use FPGA blackjack game programs, including the top-level circuit sch file gives each module using VHDL language
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori