资源列表
OSC
- It s OSC code.Verilog for MaxV.
HD_top_null
- It s HD quad code . VHDL for Altera s cyclone4
divider
- 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
sgmii_latest[1].tar
- 这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。-This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
8b10_enc
- This program is used to do encoding according to 8B/10B protocol. The program has been written in VHDL
lvboqi_demo
- 基于fpga的程控滤波器的设计，verilog写的代码-Fpga-based programmable filter design, verilog code written
dianyabiao_demo
- 基于fpga的电压表的设计，用verilog写的代码，已经过调试-Voltmeter based on fpga design with verilog write the code, it has been testing
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module
vga_controller
- 自己写的VGA的IP，avalonMM总线操作-VGA-IP, avalonMM bus operation
lcd_controller
- verilog写的LCD的ip，avalonMM总线操作-verilog LCD ip, avalonMM bus operation
DSP-with-FPGA(3rd)
- 国外权威著作-数字信号处理的FPGA实现（第三版）的源代码，包括VHDL和verilog两种格式。-Foreign authoritative writings- digital signal processing on FPGA (third edition) of the source code, including VHDL and verilog formats.
14.Anvyl_PmodDA2_Demo
- 用VHDL写的da程序，使用与xilinx开发板。-Da program written using VHDL, use and xilinx development board.