资源列表
CD1_PHOTO_ABLUM(1280)
- 在EP3C16 fpga上实现了数码相册，可以从SD卡上读取jpeg图片，并进行解码，最后在VGA显示器上显示1280*1024的图片。-In EP3C16 fpga to achieve a digital photo album that can be read from the SD card jpeg picture and decoding, and finally displayed on a VGA monitor 1280* 1024 picture.
USB_FT245
- 在altera fpga cycloneIII EP3C5E 上实现了对USB 245的通信。-In altera fpga cycloneIII EP3C5E on the realization of the USB 245 communications.
EXP42_RS232_PIANO
- 在EP3C5E上进行试验，PC机检测到PS2键盘，将键盘的数值通过串口传输给fpga，fpga驱动蜂鸣器发出音乐。-Tested on the EP3C5E, PC machine detects the PS2 keyboard, the keyboard' s numeric via the serial transmission to the fpga, fpga drive buzzer music.
voter
- 这是一个基于Quartus2 的七人投票表决系统-voter for 7 men
count4
- 这是一个基于Quartus2 开发环境的4输入加法器- 4adder basic on Quartus2
Multivibrator_circuit
- 这是某工业大学的课程设计多谐振荡电路，经过修订完全通过了的-Multivibrator circuit, Guangdong University of curriculum design
decoder_38
- 这是基于Quartus2 开发环境和verilog hdl语言写的38译码器-This is based development environment and Quartus2 verilog hdl language used to write decoder 38
encoder_83
- 这是基于Quartus 2开发环境和verilog hdl语音编译的83解码器-This is based on Quartus 2 development environment and compiler verilog hdl voice decoder 83
voter_VHDL
- 这是基于Quartus2开发环境和vhdl语音编译的表决器-voter basic on vhdl and Quartus2
matlab-and-verilog-fir4_3
- 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
verilog-generate
- 很实用的verilog中generate语句使用方法整理 -Useful in verilog generate statements use method
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners