资源列表
USB
- Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
VHDL_EPP
- 用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
vhdl-wenjian
- 这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners
vhdl-100
- 本资料中有100个vhdl的例子，是很好的学习参考资料。对于学习vhdl的人来说是很有用的。-This information has 100 vhdl example, is a good learning reference. For those who learn vhdl is very useful.
freq_meter
- Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
Habenera
- Fun little FPGA that plays a portion of Habanera
i2c
- inter integrated circuit i2c protocol
fpuvhdl
- it performs the floating point arithmetic unit
div
- it performs the serail dividing operations
MUART
- the transmitter and receiver modules for serial communication
final_10
- 10. 對於按鍵輸入密碼鎖，假設reset後，七節燈管顯示「0」，而且使用sw1、sw2二個按鍵輸入，只要按下sw1鍵，都會讓七節燈管顯示值以每秒之速度加「1」，但放開sw1鍵後就停止。-10. For the key to enter a password lock, assuming that reset after the seven lamp displays " 0" , and the use of sw1, sw2 two key input, as long as