资源列表
DM10_KX8051_LCD128X64_C5T
- FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD
DM3_KX8051_GPS_FTEST_C5T
- 这是一个基于FPGA实现的GPS的程序，保证可以用-This is an FPGA-based GPS program to ensure that you can use ... ...
DM2_KX8051_FTEST_RS232_C5T
- 这是一个FPGA的简单例程，主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
DM1_KEYs_LEDs_C5T
- 这是FPGA的一个简单例程，LED键盘显示程序，非常时候大家入门学习-This is the FPGA, a simple routine, LED keyboard display program, very time we started to learn
verilogFIR
- 基于verilog的FIR滤波器程序设计（调试过的）-verilog
1_ADDER
- vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl adder vhdl adder vhdl adder
Verilog
- 简易环形FIFO的设计、简单异步串行通信接口设计等-verilog
VHDLquickstart
- Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-Quick introduction to VHDL
clock_digital
- 用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
ddfsdemo
- 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development enviro
key
- Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. P
ActivePowerMeter
- Spartan 3e - Active Power Meter-Spartan 3e- Active Power Meter