资源列表
adder
- This the adder VHDL code, it contains input and output fild, also simulate file-adder
FSM_test
- FSM_test for textbanch in vhdl-FSM_test
fileread
- file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code
designrequirementbyvhdl
- 08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl
lab10000
- detection of the following sequence ‘10110110’in VHDL
Multiplier_Solution
- this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
verilog_2001_ref_guide
- verilog book verilog_2001_ref_guide
BasicS
- an example HDL-Core with any basic gates.
chip_sample
- SoC sample Code using Altera Xcaliber, good usefull SoC.
chuzucheVHDL
- 8出租车计价器VHDL程序与仿真有波形说明 quartus2环境-8 Taximeter VHDL program descr iption and simulation of a wave quartus2 Environment
ADC0809VHDL
- ADC0809的vhdl控制程序 有波形仿真 quartus2-ADC0809 control procedures of vhdl simulation of a wave
veriloghdl
- verilog语言书籍 夏宇闻的 十分经典 pdf 清晰版-verilog language books pdf Yu Xia Wen a very clear version of the classic