资源列表
DE2_115_WEB_SERVER_MII_ENET0
- Simple HTTP server using sockets interface of NicheStack TCP/IP and NIOS II SCPU to serve HTML, JPEG, GIF PNG, JS, CSS, SWF, content using RGMII on DE2-115 board
fpga
- FPGA控制DS18B20温度测量及显示,温度范围-20℃至100℃，精度0.1℃。数据刷新周期小于1秒。产生警报 -FPGA control DS18B20 temperature measurement and display
new-project
- 基于verilog的贪吃蛇 苹果同屏幕同时出现，贪吃蛇吃完所有苹果游戏结束，贪吃蛇的另一种写法-Based on the same screen verilog Snake Apple simultaneously, Snake eating all the apples end of the game, Snake' s another way
sine-function-generator-design
- 一个正弦发生器的设计，应用于EP2C35F672C6开发板，仿真环境为Quartus II 9.1 -A sine generator design, based on EP2C35F672C6 board. Simulated in Quartus II 9.1
3.UART_test
- FPGA的UART通信实验，已经过验证，使用verilog程序编写。-The FPGA UART communication experiment has been verified using verilog programming.
duty-cycle
- FPGA的测试占空比程序，已经过验证，自己编写，使用verilog程序-FPGA-duty test procedures have been verified, their preparation, use verilog program
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
uart_tb
- simple UART testbench code.inlucding
uart_if
- ram source read mode UART CODES.
PLL
- 基于FPGA的锁相环应用，原理图输入法，较为直观，锁相的效果无抖动-FPGA-based PLL applications, schematics input method, more intuitive, the effect of jitter PLL
jiaotongxinhao
- vhdl语言编写的，在QuartusII下，交通信号灯控制器-vhdl language, in QuartusII, the traffic signal controller
ledarray
- 用vhdl语言,在QuartusII下,点阵显示欢迎使用系统-Using vhdl in QuartusII, the dot matrix display welcome to use the system