资源列表
DE2_Top
- altera DE2 开发板的重要应用接口，包括VGA，以太网通信，音频和视频解码，后续开发例程时可以直接使用其中的端口-altera DE2 development board important application interfaces, including VGA, Ethernet communications, audio and video decoding, the subsequent development of routines which can be used dir
DE2_NIOS_HOST_MOUSE_VGA
- VGA显示器和鼠标的联合应用，演示了怎样利用鼠标控制VGA显示器上的图像-VGA monitor and mouse combination, demonstrates how to use the mouse to control the image on the VGA monitor
DE2_SD_Card_Audio
- SD卡和音频解码装置的联合例程，使用环境为altera DE2开发板，可以直接编译使用-SD card and audio decoding apparatus combined routines, using the environment as altera DE2 development board can be directly compiled to use
DE2_USB_API
- 基于altera DE2开发板的USB应用程序，可以实现对FPGA的各项控制，包括输入数据到SRAM中，更换VGA显示器显示的图片等-Based on altera DE2 development board USB application process can be achieved with the control of the FPGA, including the input data to the SRAM, the replacement of VGA display pictur
DE2_NET
- altera DE2开发板和网络通信的例程，使用了nios ii系统-altera DE2 development board and network communication routines, using nios ii system
div_clk
- verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
clk
- 五分频时钟的产生,分为两个，一个是不带边缘检测，另外一个带边缘检测-Fifth generation of the clock frequency is divided into two, one is a non-edge detection, and the other with edge detection
DE2_Top
- 此设计是一个裸机的设计，其中包含在DE2开发板所有的引脚分配。它还包含一个与所有的对应于每个引脚的输入/输出端口的Verilog模块。这可以被用来作为一个起点上的电路板的设计。-This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output por
Rs232Memory
- 使用ram 进行rs232 通信 非常实用-Using ram for rs232 communication
16bit_ram
- 利用vhdl语言在fpga实现十六位的ram 使用非常方便-Using vhdl fpga implementation sixteen languages in the ram is very convenient to use
ramipcore
- 使用vhdl 语言在fpga环境下实现ram ip core-Environment in fpga vhdl language used to achieve ram ip core