资源列表
zr36060.tar
- vhdlsource code for jpegpack
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
TFT
- FPGA EP1C6Q208C8实验。使用FPGA直接控制TFT彩屏，达到显示RGB。有仿真波形。-FPGA EP1C6Q208C8 experiment. Use the FPGA control to display TFT screen, RGB. A simulation waveform.
traffic-light-vhdl-Quartus-II6.0
- 简单的交通灯vhdl程序 Quartus II6.0下的程序 包含图形仿真-easy traffic light vhdl Quartus II6.0
fifo
- 同步fifo和异步fifo程序，含时钟同步。运用格雷码-Synchronous FIFO and asynchronous FIFO FIFO procedures, including clock synchronization. Application of gray code
exp1_CountWithMemory
- 用Altera—DE2板实现秒表的功能，该秒表具有一个复位按钮，两个暂停按钮和两个记录按钮。-Stopwatch function using Altera-DE2 board, the stopwatch has a reset button, two buttons and two recording pause button.
response_time
- 在fpga开发板上实现一个测试人的反映速度的功能，当灯亮时，按下按键，灯灭，然后数码管显示灯从亮到灭的时间，也就是人的反应时间-In fpga development board to implement a test reflect the speed of people' s function, when lights, press the button, the lamp is off, then the digital display lights from bright to o
eth_Management_interface
- FPGA verilog simple MAC 源码-FPGA verilog simple MAC source code
xx_float_add
- 32bit浮点数加法。只实现了两个正数的相加，通过modelsim仿真。开发环境为 Xilinx ISE。-32bit floating point adder. Only realized the sum of two positive numbers through modelsim simulation. Development environment for Xilinx ISE.
chaoshengbo
- 超声波测距单元，在测距完成后在8位数码管上显示测距结果，可用于小车防撞。-Ultrasonic Ranging unit can be used for car crash
rtl
- 通过FPGA对pll进行控制，改变PLL 的输出频率。接口为spi接口。-Pll controlled by FPGA on changing PLL Output frequency. Interface spi interface.
crc
- 一种另类的crc生成办法，改变了流水先结构而使用并行结构。可拓展思路。-An alternative way to generate crc, changing the water first structure to use parallel structures. To develop ideas.