资源列表
piaobiao
- 数字跑表，具有复位、暂停、秒表计时等功能。有三个输入端，为时钟输入(clk)、复位(clr)、启动与暂停(pause)。-Digital stopwatch, with reset, pause, stopwatch functions. There are three inputs for clock input (clk), Reset (clr), start and pause (pause).
sin_cic
- 毕设时用Verilog编写的CIC滤波，包含输入正弦信号，-Verilog CIC
MPSK-modulation-VHDL-
- MPSK调制与解调VHDL程序与仿真，本文为DOC文档，附有源码和仿真波形-MPSK modulation and demodulation VHDL program and simulation, this paper for the DOC document, attached to the source code and simulation waveform
elevator-controller-VHDL
- 电梯控制器程序设计与仿真，本文为DOC文档，附有源码和仿真波形-The elevator controller programming and simulation, this paper for the DOC document, attached to the source code and simulation waveform
frequency-measuring-VHDL
- 采用等精度测频原理的频率计程序与仿真，本文为DOC文档，附有源码和仿真波形-Equal precision frequency measuring principle of frequency meter program and simulation, this paper for the DOC document, attached to the source code and simulation waveform
Frequency-meter-VHDL
- 频率计程序设计与仿真。本文为DOC文档，附有源码和仿真波形，详见文档-Frequency meter program design and simulation, this paper for the DOC document, attached to the source code and simulation waveform
PSK-modulation-VHDL
- PSK调制与解调VHDL程序及仿真，本文为DOC文档，附有源码和仿真波形-PSK modulation and demodulation VHDL program and simulation, this paper for the DOC document, attached to the source code and simulation waveform
URAT-VHDL
- URAT VHDL程序与仿真，本文为DOC文档，附有源码和仿真波形-URAT VHDL program and simulation, this paper for the DOC document, attached to the source code and simulation waveform
rms_cal
- 基于VHDL的有效值求取，内含低通滤波子模块-RAM CAL with LPF by VDHL
bresenham-algorithm
- Bresenham algorithm code, on verilog language using a Spartan 3
FA
- 使用VERILOG實現全加器的設計,並附上TB供測試-Use VERILOG achieve full adder design, together with a test for TB
timer
- 使用VERILOG實現時鐘,並附上TB供測試-Use VERILOG realize the clock, along with tests for TB