资源列表
single_port_ram
- Single port RAM file VHDL source code
dds
- 可以实现通过串口对DDS进行配置，单音模式，输出频率为50M。已经调试过，直接可以使用-Can be achieved via a serial port configuration of DDS, mono mode, the output frequency is 50 m.Have been debugging, can use directly
MUSIC-FPGA
- altera fpga quartus simulation environment MUSIC algorithm example package with all necessary files including all past year research papers concluded for literature review-altera fpga quartus simulation environment MUSIC algorithm example package wit
FPGA-I2C[Verilog]
- 基于FPGA平台的I2C通信代码 Verilog编写-Based on FPGA platform of I2C communication Verilog code to write
RGB-color-bar[Verilog]
- 基于FPGA的 VGA彩条试验 Verilog-Verilog VGA color bar test based on FPGA
sdram_controller
- sdram的控制器代码 sdram的控制器代码 sdram的控制器代码-sdram controller
decimal_divider_nr_norm
- - non-restoring like divider. As in Paper. -- For normalized numbers -- non-restoring like divider. As in Paper. -- For normalized numbers ---------------------------------------------------------------------------------
DE0_NANO_VGA
- ntity DE0_NANO is Port ( CLOCK_50 : in STD_LOGIC --//////////// LED ////////// LED : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- --//////////// KEY ////////// KEY : in STD_LOGIC_VECTOR(1 DOWNTO 0) -- --//////////// SW ////////// S
dianziqin2--lcd
- 基于Altera公司的开发板DE2--EP2C35F672C6，制作的电子琴，实现do、re、mi、fa、sol、la、xi、do八个音调，并可选择手动或自动播放，其中手动播放可实现存储与回放。并可实现液晶屏对音符的显示。-Development board based on Altera' s DE2- EP2C35F672C6, making organ, realize do, re, mi, fa, sol, la, xi, do eight tones, and can choo
RLS-Algorithm
- I am giving new files related to RLS algorithm
CRC_test
- 基于verilog编写的CRC校验程序，采用LFSR电路实现。-CRC verilog
kcpsm3
- main VHDL entity for PicoBlaze chip control