资源列表
yima
- 很简单的译码器，实现四位输入，完成0-9数码管显示，简单好用-A very simple decoder to achieve four inputs, 0-9 to complete the digital tube display, simple and easy to use
bram_delay
- Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
Ipcoredesign
- 微电子/软硬IP核设计：IP核脚本指南，模型开发指南-Microelectronics/soft and hard IP core design: IP core scr ipting Guide, Model Development Guide
counter
- 从0到14的计数，当然你改动下源程序，计数范围可以扩大。还带有清零的功能！-From 0 to 14 counts, of course, you change the next source, counts could be expanded. Also with the Clear function!
vhd
- vhdl课件，基础教程，简单入门，适合初学者学习- useful
PPT-VHDL
- VHDL语言与系统实践，PPT教程共6章-VHDL language and system of practice, PPT tutorial a total of six chapters
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计 库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test benc
tips_vhdl
- 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序，供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
state_mm
- 有限状态机源码，verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation.
cpu_4
- 用verlog语言写的4指令CPU的实现，运行于MAX+plusII10.2环境下-Written in four languages with verlog instruction CPU implementation, running on the MAX+ plusII10.2 environment
Signal2
- VHDL语言写的序列信号发生器，放心使用，没问题-VHDL code