资源列表
rs2322
- The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
VHDL_flash
- vhdl chip design a very good design
VHDL_Codes
- vhdl codes of basic components
111
- Verilog语言编写的循环彩灯控制器 这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
Shortest_job_first
- 短作业优先级算法（在VS2005中，可以自己创建各进程的运行时间，导入后能够运行，）-shortest job first（）
max197
- FPGA实现MAX197读写程序，经过验证-FPGA control 12bAD max197
daq_arm_fifo
- 实现FPGA与ARM的通信，数据、地址总线方式-FPGA（xilinx） and the ARM（三星2440） implementation of communications, data and address bus mode
TheDifferencebetweenVHDlandVerologHDL
- VHDL与Verolog HDL具体的不同，包括整体结构，数据对象及类型，运算符号，语句子结构，附加结构等-The Difference between VHDl and Verolog HDL
miaobiao
- VHDL语言实现的秒表设计，具有分秒，计数清零等功能-VHDL language implementation of the stopwatch design, with the minutes and seconds, counting functions such as Clear
calculator
- 此源码为在xilinx环境中用VHDL实现计算器，实例可用xcs40xl-4-pq208戓xc2s100-6pq208FPGA来实现-The source code in xilinx environment using VHDL implementation calculators, examples can be xcs40xl-4-pq208 Ge xc2s100-6pq208FPGA to achieve
bist
- design for test Test and Design-for-Test for memory bist-design for test
Ringcounter
- ringcounter verilog HDL example code