资源列表
idt723641
- VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use
PID-controller
- 用VHDL设计的PID控制器，带有VHDL测试平台代码-PID controller designed with VHDL,with VHDL testbench code.
divider
- 用VHDL编写的多次分频器，带有VHDL测试平台代码-Multiple frequency divider with VHDL testbench code
MCU_to_FPGA
- FPGA与单片机通信的代码，采用VHDL编写，已验证过-FPGA and MCU communication code, the preparation of VHDL has been verified
lcd_12864
- lcd12864带中文字库的显示程序，采用状态机的方式实现，已验证过的-lcd12864 with the Chinese character display program, using the state machine ways, has been verified
Frequency_8bit
- 基于FPGA的8位数字频率计，经过本人验证，误差很小，结果通过数码管显示（完整的工程）-8 FPGA-based digital frequency meter, after I verified, the error is very small, the results through the digital display (complete works)
CodedLOCK
- 基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释-FPGA-based design and implementation of electronic locks, language is VHDL language, annotated
ManchesterCode
- VHDL编写的曼彻斯特编码程序，已验证通过，文件为完整的工程-VHDL, Manchester coding process has been verified through the file for the complete project
Embedded-Systems-Lab-2
- Configure your altera fpga and get features explored
generate-coordinates
- 使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。-Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive numb
EDA-experimental-guide-book
- 利用QUARTUS II 8.1软件进行简单的EDA设计。该实验指导书原理阐述清楚，内容详尽，实验过程描述清楚，每一个实验步骤都有具体的截图。该实验指导书包括四个基本实验：实验1 QUARTUS II 8.1软件的使用；实验2 图形法设计24进制计数器；实验3 60进制计数器；实验4 简易数字钟。-Use QUARTUS II 8.1 software for simple EDA design. The experiment instructions Rationale clear, deta
Desktop
- 频率检测，verilog hdl,单片机用C8051F120外部中断0。测量范围2Hz到9MHz-Frequency detection, verilog hdl, C8051F120 microcontroller with external interrupt 0. Measuring range 2Hz to 9MHz