资源列表
top_module
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，设计的4个led灯分别实现不同功能，然后由一个顶层文件调用，完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called,
WASHING-MACHINE-2012Verilog
- Verilog语言编写的自动洗衣机控制程序，数字系统课程设计-Verilog language automatic washing machine control program, digital systems curriculum design
FIFO
- Simulation and Synthesis Techniques for Asynchronous FIFO Design
ADC
- CPLD ADC采集控制源码CPLD ADC采集控制源码-CPLD ADC
CummingsSNUG2002SJ_FIFO2
- Simulation and Synthesis Techniques for Asynchronous FIFO Design2
manchester
- manchester ABOUT CPLD 应用数字通信应用端口-manchester ABOUT CPLD
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
counters
- 用VHDL编写的最大值为255的计数器，供初学者参考-A 255 counter of VHDL，for Beginners Reference
conditioner
- VHDL设计的空调系统有限状态自动机，带有VHDL测试平台代码-VHDL design of air-conditioning systems finite state automata with VHDL testbench code
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder