资源列表
FIR_dida
- 自己写的FIR滤波器设计，verilog语言写的，很好用-Write your own FIR filter design, verilog language, easy to use
fre_test_chenshuo
- fpga的等精度测频程序，很准确，最少可以控制到0.1hz到47M,-fpga and other precision frequency measurement procedures, very accurate, at least can be controlled to 0.1hz to 47M,
SDRAM_verilog@tequan
- 本资源是特权同学编写的sdram控制器，包括数据读写，串口输出，很有学习价值-This resource is privileged students write sdram controller, including data read and write, serial port output, is worth learning
spi_stm32
- 本程序使用verilog hdl 语言编写的SPI程序，可与stm32进行数据的传输-This program uses SPI verilog hdl language program with stm32 for data transmission
CPLDpro
- 模拟量输入卡CPLD程序，包括比较器，计数器等。-Analog Input Card CPLD procedures, including comparators, counters and so on.
巴克码VHDL
- 非常详尽的VHDL语言编写的巴克码发生器，已在QuartusII上运行，检查无误
MATLABPQPSK_final
- QPSK调制解调，载波同步的matlab源程序，测试通过无bug-QPSK modulation and demodulation, carrier synchronization matlab source code, test bug-
FPGA
- fpga实现图像的变换，图像旋转放大-fpga implementation image transform, image rotation and magnification
CPLD-FPGA
- CPLD FPGA嵌入式应用开发技术白金手册配套源码-CPLD FPGA embedded application development technology platinum manual matching the source code
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
keyqudou
- fpga verilog hdl 设计键盘去抖动程序，设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit