资源列表
SDRAM_controler_code
- SDRAM的verilog控制器代码极其仿真模块-The verilog code for SDRAM controller is extremely Simulation Module
flash_rom
- flash_rom 将拥护数据存储在flash_rom中，然后读取flash_rom里面的数据-write and read flash_rom
dds_key_bak
- DDS控制部分 数码管显示，可选择多种波形，频率可控-DDS control part of digital tube display, choose a variety of waveforms, frequency controlled
Xilinx_yuanyu
- 本文详细介绍了xinlinx公司fpga的原语使用方法，原语相对于调用核来说更简单明了，推荐初学者多使用原语-This paper describes the xinlinx' s fpga use the original language, the original language as opposed to call-core is more simple and straightforward, it is recommended for beginners to use mor
SpartanIIE_DLL
- 本文详细介绍了SpartanIIE 内部锁相环（DLL）的使用，方便初学者-This paper describes the SpartanIIE internal phase-locked loop (DLL) for use, easy for beginners
DS1302
- 本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可-This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays
VHDL_i2cs_CPLD
- 占用寄存器超少的,I2C从模式的代码的VHDL源代码,很有用哦!-Occupation register ultra-small, I2C slave mode code VHDL source code, useful Oh!
VHDL
- 基于vhdl数控分频器的设计与应用，少有的关于分频方法的介绍-Divider based on vhdl design and application of NC
ctrller
- 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
ele_clock
- 时钟（时分秒LED显示） 秒表（计时） 闹钟（自动报时）-alarm clock
ADC0809
- 完整ADC0809的时序，采用VHDL语言编写，在Altera cycloneI/II系列下的EP1C6\EP2C5\8平台下测试完成，稳定-ADC0809 Driver by VHDL
double_shifter6
- 带置位的双向移位串入/并出6位移位寄存器。-With a string of set-bit bi-directional shift into/and a 6-bit shift register.