资源列表
FPGA_Counter
- 利用FPGA设计的可以自适应的频率计，里面有详细的文档介绍。-FPGA designs can use adaptive frequency counter, which document describes in detail.
FrequencySpectrum
- 基于ep1c6q240c8 fpga 及msp430fg4618混合控制器的频谱分析仪控制代码-Based on ep1c6q240c8 fpga and msp430fg4618 Hybrid Controller spectrum analyzer control code
200998301FSK
- 基于FPGA的利用FSK调制方式的无线传输系统中的短信息发送传输接收，对无线传输的学习有很大帮助！-FPGA-based FSK modulation used for wireless transmission system to send the short message transmission to receive, for wireless transmission of great help to learn!
FPGA
- 华为的基于XILINX公司FPGA器件的高级设计应用.可以帮助放大工程师对FPGA的开发有一个更新的认识.-Huawei, based on XILINX' s FPGA devices advanced design applications. FPGA engineers can help to enlarge the development of an updated understanding.
VHDL
- 一本VHDL语言的快速入门书籍.该书由多年工作在产品开发一线的工程师编写,适合初学者对VHDL语言有一个快速的认识和应用.-A VHDL language Quick Start book. Book from many years of working in the forefront of product development engineers to prepare, suitable for beginners to the VHDL language a quick understa
verilog-VGA
- 在FPGA内，实现简单的VGA显示功能。verilog源代码-In the FPGA, the realization of a simple VGA display. verilog source code
FPGA-IIC
- 在FPGA内，实现IIC数据接口。verilog源代码-In the FPGA, the realization of IIC data interfaces. verilog source code
verilog
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。 Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模语言。此外，Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
XILINX
- Verilog汇编很牛叉 O(∩_∩)O哈哈哈~-Verilog
EXP-EPM3128_3256
- cpld/fpga芯片exp-epm3128/3256的详细说明，适用于quartus以及maxplus软件-cpld/fpga chip exp-epm3128/3256 a detailed descr iption of the software for quartus and maxplus
Test_Plg_18
- 基于FPGA的等精度频率测试仪,测量范围1HZ到100M.已调试成功.采用康芯公司的FPGA开发板,嵌入51内核程序.-FPGA-based test instrument such as the frequency accuracy, measurement range 1HZ to 100M. Has been a successful debugging. Using Kang' s FPGA core development board, embedded in 51 kernel