资源列表
huawei_FPGA_design_flow
- 有关华为的fpga 设计流程，内部资料，希望对各位同仁有所帮助-fpga design flow of huawei
LAB27
- 基于FPGA的1K分频模块，输入为24MHZ的时钟信号-1K points frequency FPGA-based modules, the clock signal input 24MHZ
Mars-EP1C6-F_code3
- 此包为FPGA学习板的综合实验程序源代码,包括两个实验:交通灯和数字时钟.-This packet FPGA board to study a comprehensive experimental program source code, including two experiments: the traffic lights and digital clock.
Mars-EP1C6-F_code2
- 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD,
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, mul
modelsim
- 用verilog编写的基于流水线结构的16阶滤波器的实现 -filter
bram_block_0_wrapper
- 赛灵思FPGA开发板上BRAM模块VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board BRAM module VHDL source code, hardware design can be used as reference!
debug_module_wrapper
- 赛灵思FPGA开发板上调试模块的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board debug module' s VHDL source code, hardware design can be used as reference!
clock_generator_0_wrapper
- 赛灵思FPGA开发板上时钟源的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board clock source of the VHDL source code, hardware design can be used as reference!
dip_switch_wrapper
- 赛灵思开发板dip开关的VHDL源代码，对于硬件开发参考的材料！-Xilinx development board dip switches, VHDL source code for the hardware development of reference materials!
pushbutton_wrapper
- 赛灵思FPAG开发板上的按钮VHDL源代码，对于硬件设计可以借鉴的好材料！-Xilinx development board FPAG button VHDL source code for the hardware design can learn from the good material!
pid_vhdl_code
- PID controller... ... ... ... ... ... ... ... ..... -PID controller.....................................................