资源列表
Altera-verilog-I2C
- I2c verilog语言，在开发板上验证过的FPGA端代码程序；(Altera flatform, use verilog code i2c, test ok.)
spi_slave_test
- 实现spi协议的从机代码，亲测可用。按照字节接收，发送可以实现一次发送19字节，可按照需要更改。(The implementation of the code of the SPI slave protocol is available. By byte received, sending can be sent to send 19 bytes at a time, which can be changed as needed.)
intro_40nm_xcvr_portfolio_finaledit_cn
- Altera的40-nm收发器系列产品, 发展趋势和挑战
shiboqiFPGA
- 本文是基于2009年国赛题目数字示波器的题目分析以及整体实现的方法比较，具有很大的使用价值-This article is based on the 2009 state title game digital oscilloscope analysis of the subject and the overall implementation of the method is, of great use value
dds
- 这是一个基于ＦＰＧＡ设计的ＤＤＳ信号发生器设计。能够生成正弦波＼ＡＳＫ＼ＰＳＫ＼ＡＭ＼ＦＭ等波形。-This is an FPGA design of DDS signal generator based on. Capable of generating sine \ASK\PSK\AM\FM and other waveforms.
Post_simulation_based_QuartusII_ModelSimSE(Verilog
- 详细的讲解了怎样利用modelsim进行后仿真，对初学者很有帮助。-In detail how to use modelsim post-simulation, helpful for beginners.
dianti1
- 该程序是一个简单的电梯控制程序,运用VHDL语言编程,能实现电梯所要的功能并在DE2板上演示-The program is a simple elevator control procedures, the use of VHDL language programming, to achieve the desired function of the elevator and in the DE2 board demo
UART_DMA
- 实用串口与SDRAM控制接口VHDL语言程序代码-Utility serial port and SDRAM control interface VHDL language code
B_to_D
- 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
CoreSPI
- 数字电子设计fpga设计的spi接口的ip_core，可以直接用于在fpga设计，支持actel的fpga芯片，支持主从模式，fifo大小可选。-Fpga design of digital electronic design spi interface ip_core, fpga design can be directly used to support actel the fpga chip, support master-slave mode, fifo size options.
TaxiMeter
- 出租车计价器；包括计价，计时，计公里数，实时显示-The Taximeter including pricing, timing, total mileage, real-time display
cordic
- ise下用verilog实现的cordic算法的实现程序-ise under cordic algorithm verilog achieved with implementation of the program