资源列表
uartlcd
- 通过FPGA的VHDL程序实现对1602液晶的控制，此模块可以作为IP核直接调用-By FPGA VHDL program to achieve the 1602 LCD control module can be called directly as an IP core
Freq_gen
- XILINX 分频器 100MHz，1KHz， 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is
DDS-baseenerator
- 基于DDS的多模信号发生器设计DDS-based design of multi-mode signal generator-DDS-based design of multi-mode signal generator
clock
- vhdl经典源代码——时钟设计，入门者必须掌握-vhdl classical source code -- Clock Design, beginners must master
paobiao
- 用verilog 编写的数码管显示的秒表-Prepared using verilog digital display of stopwatch
SIN-MODULATE-BASED-FPGA
- 对正弦波进行调制，下载到FPGA的硬件环境中，运行后用示波器检测，结果可行-On the sine wave modulation, downloaded to the FPGA hardware environment, running with an oscilloscope, and the results feasible
DDS
- 基于Altera CycloneII 21eda公司开发板的直接数字频率合成器DDS的代码。生成信号波形形状和频率均可调-Altera CycloneII 21eda company based development board direct digital frequency synthesizer DDS code. Generate the signal waveform shape and frequency can be adjusted
clock_shiyan
- 数电课程设计，数字时钟，基于Quartus II设计(Digital electric course design, digital clock)
Next186_SoC_DE2-115_Quartus15.1_09Feb2017
- Next186 x86 for DE2-115
简单智能车VHDL实现
- FPGA实现智能车利用红外传感器使小车沿预定轨道平稳行驶，数码管显示障碍物与小车的距离，距离低于某值则停止运行
oscilloscope_using_FPGA
- verilog实际例子，非常适合初学者学习-verilog practical examples, very suitable for beginners to learn