资源列表
Voip-SIP-Telephone
- 网络电话。哥伦比亚大学CSEE 4840课程设计-Internet telephony. Columbia University CSEE 4840 Course Design
DDR_SDRAM_controller
- ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
MUSIC
- 基于FPGA的音乐实验，实现音乐的播放，非常美妙-FPGA-based experimental music and realize the music player, very nice
24xiaoshijishuqi
- 用verilog编写的24小时计数器，可以用作电子时钟，简单易懂。-Written in verilog 24 hour counter, which can be used as electronic clock, easy to understand.
MAX1487-MAX491_cn
- MAX1487到MAX491的芯片资料（中文版），其中包括MAX489-MAX1487 MAX491 chip data (Chinese Edition), including the MAX489
ddr
- ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Verilog
- 硬件描述语言Verilog-Verilog hardware descr iption language
eda
- 有关vhdl语言的例子，很简单，不过看完后会收获很大-Examples of the vhdl language is very simple, but after reading a great harvest
DZZ1
- 多功能数字钟 能进行正常的时、分、秒计时功能, 分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。 2. 能利用实验系统上的按键实现“校时”“校分”功能： 3. 能利用扬声器做整点报时-VHDL
DAC(tlv5618)
- 本设计是基于EP4CE15F17C8N和TLV5618的双路12位DAC模数转换和12864显示的程序-The design is based on a program EP4CE15F17C8N and TLV5618 Dual 12-bit DAC analog to digital conversion and display of 12864
SDRham-LA3BO
- AHDL Tutorial Power Point Presentation.
shuzizhong
- 用VHDL实现数字钟的设计，可显示时分秒，并可调-Digital clock with VHDL design, you can display minutes and seconds, and adjustable