资源列表
SDRAMcontrol
- 用VHDL编写的SDRAM控制器，能实现SDRAM的读写控制及片选。-Prepared using VHDL SDRAM controller, able to SDRAM read and write control and chip select.
fir滤波器设计
- 详细介绍了，给予FPGA设计fir滤波器，里面有详尽的VHDL代码。
MaxPlus
- 硬件设计语言-Hardware design language
FPGA_and_modelsim
- 新手入门FPGA资料，了解FPGA的开发全过程，对开发的流程有清晰的认识。介绍modelsim 的使用，让你熟练使用modelsim加速设计。-Getting Started FPGA to better understand the whole process of the development of FPGA on the development of a clear understanding of the process. Introduced the use modelsim, so
clock_digital
- 用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
AHDL_language_basic
- AHDL语言_08_09_16嵌入式编程系列丛书-AHDL series embedded programming language _08_09_16
AHDL
- AHDL教程 硬件描述语言,Altera 的硬件描述语言AHDL,AHDL电路设计举例-Hardware descr iption language AHDL, Altera hardware descr iption language AHDL, AHDL circuit design example
fir_test
- 采用xilinx进行的FPGA的FIR滤波器设计-Conducted using xilinx FPGA FIR filter design
TaxiCnter
- 用Xilinx91i模块，设计开发的出租车计价器，功能完整-Use Xilinx91i module design and development of the taxi meter, full-featured
RGB_TV__dataconverter
- TV converter based on EPM3064ATC44, for display digital data, Altera source code, PCAD source files
on-chip-power
- ON CHIP POWER OPTIMIZATIOM
CLOCK
- 对78M时钟通过倍频和分频分别实现2.048MHz与8KHz FP信号，同时可以对时钟信号进行精确计数。-On the 78M clock multiplication and division, respectively, through the realization of 2.048MHz with 8KHz FP signal, clock signal can be accurately counted.