资源列表
xuljc
- FPGA编程，用Verilog语言实现序列检测功能-The FPGA programming, using Verilog language implementation sequence detection
clock_VHDL
- 主要供学习FPGA的人员学习如何写VHDL程序之用，该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
signal
- EP2C5Q208C8 verilog 产生m序列 50M晶振分频得到时钟，可以选择10种时钟- -！-EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
GetPcmSim
- PCM数据采集，CPLD部分。 写了很长时间了。 通过串口传送到PC。
DE1_SD_Card_Audio
- SD卡操作模块，一个简单的sd卡使用实例
WajidMunir258
- This a lab of processor-This is a lab of processor
RS232(1)
- 基于FPGA的串行通信接口设计，用硬件描述语言VHDL实现-FPGA-based serial communication interface design, using hardware descr iption language VHDL implementation
pingponggames
- 乒乓球游戏机的设计，采用VHDL语言编写，有完整的设计要求，以及系统的实现完整代码-Table tennis game design using VHDL language, complete the design requirements, as well as the realization of the complete code
DE2_70_CAMERA_v1.0.2
- 應用程式verilog相關事件，參考文件-Verilog application related events, refer to documents ... etc.
ADP5052.PDF
- 多路稳压输出，可配置个电压，非常适合用于fpga电源-Multiple regulated output voltage can be configured very suitable for fpga power
motor
- verilog motor control