资源列表
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
keypad_16_keys_interface
- This code its referent a keryboard matricial
exp03_PCI
- PCI设备查询及其配置空间的读取,Win9X/me下可以用,显示数据含义可查看PCI22规范中的介绍-inquiries and equipment PCI configuration space read, Win9X/me can use. display data access PCI22 meaning of the norms introduced
sync_fifo
- 一种同步的先入先出verilog程序，可正确地通过编译-a programe of fifo wrote by verilog
pljcx
- 测频控制 锁存器 计数器 顶层文件 -Frequency counter top-level file control latch
ParallelScrablerDescrambler
- VHDL code for parallel 6-bit scrambler and descrambler
pwm_hw
- sopc nios ii学习资料介绍niosii 开发自定义外设pwm的verilog源代码-Learning sopc nios ii information on the development of custom peripherals niosii the verilog source code pwm
步进电机及伺服电机的控制
- 本程序采用vhdl语言对步进电机及伺服电机进行控制，控制方式灵活，有变速，正反转，显示等多个模块-This procedure using VHDL language of stepper motor and servo motor control, control flexibility, have variable speed, positive, showing a number of modules, etc.
UART_verilog
- 电脑发数据，CPLD接收后会送电脑的，verilog程序，可以直接使用-Computer to send data, the CPLD will be sent after receiving the computer, Verilog program can be used directly
Uart_Send
- UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
synthesize--fit--simulation
- 关于FPGA 设计的流程过程的综合，适配，仿真名词的解释，以及相关注意事项-The attention of the process of FPGA
64697923ADC0809_VHDL_ctrl
- 数模转换控制器ADC0809的verilog代码-the verilog code of ADC0809