资源列表
aulto
- 自動販賣機控制電路,具有累計輸入金額和商品控制輸出和自動找零。-Vending machine control circuit, with a total amount of input and control output of goods and give change automatically.
count
- 各种常用计数器模块，加减可控计数器和模可变计数器等等，经过仿真得到了正确的波形-Various common counter module, subtraction controllable variable modulus counter counter and so on, through simulation to get the correct waveform
seven
- seven.vhd 七人表决器VHDL源码 七人表决器.doc 程序说明-seven.vhd seven votes for VHDL source code for seven votes. A descr iption of the procedures for doc
32位超前进位加法器（verilog）
- 淘的32位超前进位加法器（verilog），已验证
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
vhdl
- RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
chap8
- 常用经典典型电路，如全加器，乘法器，如何减小资源
vga-timing-generator
- VGA时序产生，可用于VGA接口的时序控制-VGA Timing Generator
cordic
- VHDL实现cordic算法，精确度非常高，模块化设计，带显示功能-VHDL implementation cordic algorithm, a very high accuracy, modular design, with display function
1212
- VERILOG+HDL硬件描述语言实现电话计费系统，实践代码。-VERILOG+ HDL hardware descr iption language telephone billing system, practice code.
verilog
- 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
Support-TP-CCIN-2012-2013
- VHDL编辑PGCD的文件。实际上，这是上课时候老师给的。求通过验证-VHDL edit file of PGCD. In fact, this is the teacher gave during the class. Requirements through validation.