资源列表
watchdog
- 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。-Watchdog verilog source.
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
wallace14
- this is wallace multiplier 14 bit in vhdl code
Control
- Datapath Controller verilog code
DDSverilog
- 基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者-ＤＤＳ based on Verilog ＤＨＬ for FPGA
traffic-light-controller
- 交通灯控制器源程序，使用VHDL编写，在系统上实验通过- The traffic light controller source code, the use of VHDL to write, on the system by experiment
LCD_TEST
- LCD_test.用来测试LCD的显示。已经用在DE2开发办上了，可以用
leddisplay
- microblaze打包文件，功能是在led上显示的管脚说明-microblaze packaged file
multicycle-MIPS
- multicycle MIPS with multiplier verilog implementation
vga_controller
- VGA controller in verilog
vdl
- 基于EDA控制LED液晶屏幕的程序，显示彩条屏幕-EDA program to control the LED LCD screen, display the color bar screen
2
- ADC0809 VHDL控制程序，实现简单-ADC 0809 VHDL control procedures, simple