资源列表
firewire
- test former partlelr list
cascaded_adder
- implementation of cascade adder with verilog plus testbench
ISE_lab17
- 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal gene
shiyan2
- 串口发送，通过拨码开关表示传输的数据，并在数码管显示发送数据-Serial port to send data transmitted via DIP switch, and send data in digital display
vga
- VGA graphic controller Verilog Source Code
clock
- 基于Verilog的数字时钟的源代码 用quartusII7.2软件仿真通过-Verilog-based digital clock
SRC_2CH
- 2通道HDCVI视频光端机：实现两个高速AD转换采集HDCVI信号，编码扰码后通过光纤远距离传输，对端收到后解码通过高速DA转换为HDCVI信号。-2 channel HDCVI video Guangduan Ji: two high-speed AD acquisition signal conversion HDCVI, scrambling code via the optical fiber remote transmission, receives an end after deco
sy6
- 数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图-Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic
ROM_based_sine_wave_generator_VHDL_design
- VHDL基于ROM的正弦波发生器的设计的实验报告，内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
sim_tb_top
- DDR2用软件自动生成的启动代码，是使用不可少的~-DDR2 start automatically generated by software code, is the use of essential ~
89_full_adder
- vhdl 语言 开发 程序比较详尽 微处理器 里面的部件-vhdl language development program inside the more detailed parts of the microprocessor
Verilog_32bit_Adder
- 32位超前进位加法器的改进Verilog实现-Improved Verilog implementation of 32 bit ahead carry adder