资源列表
alpha1_3_compensator
- 同為適用於1.8V轉1.3V必迴路 在1Mhz頻率下 RLC各為 25m 4.7u 10u 排除浮點數的int整數補償器 給有需要的同學作為參考-The same applies to 1.8V 1.3V will turn 1Mhz frequency RLC circuit at each 25m 4.7u 10u exclude floating point int integer compensation to needy students as a reference
ComparatorTestVersion
- 基於wire方式設計的補償器,但需外接DFF依照同學想做幾階的可在進行外加,Z^-1 需2個 Z^-2 3個依此類推.僅提供實做參考,實際參數需自行設計-Based on wire mode compensator design, but need to add DFF in accordance with the order of a few students want to be carrying plus, Z ^-1 need two Z ^-2 3 one, and so on. Pr
timing_sim
- 使用ModelSim对Altera设计进行时序仿真的简单操作步骤-Simple operation steps using the ModelSim timing simulation for Altera design
Example-b8-3
- 使用DO文件进行仿真的基本方法,包含基本操作步骤-The basic method of using DO file for simulation，include basic steps
Example-b8-4
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看-Comparison of the ModelSim wave functions , compare the results can be viewed on the waveform window or the list window
Example-b8-5
- 四态的VCD文件，参数在0/1/X/Z之间变化，没有信号的强度信息-The four state VCD file, parameter changes between 0/1/X/Z, no intensity information of the signal
Example-b8-6
- Synplify Pro综合流程，体会Synplify Pro综合工具的使用方法与技-Synplify Pro synthesis process, and technology usage experience of Synplify Pro synthesis tool
da
- distributed arithmetic based fir filter implementation by xilinx using system generator
important
- importatn document for fir filter implementation by distributed arithmetic
gailiangban
- 基于fpga的平台，用verilog，写的一个可以表白的工具-can be use to show love
counter60
- this a counter. it can count from 0 to 50-this is a counter. it can count from 0 to 50
EDA
- 里面包含各种基于赛灵思公司的一些考试应用小程序及一个电梯控制系统的设计。-Which contains a variety of exams based on Xilinx some applets and an elevator control system design.