资源列表
fenpinqi
- verilog写的分频器，其最高频率为输入频率，没毛刺，挺好-written in verilog divider, the maximum frequency of input frequency, no glitches, very good
fpganios
- fpga制作的逻辑分析仪 nios2控制系统 自己的科创论文 绝对有用-produced fpga logic analyzer control system nios2 Branch' s own record is absolutely useful papers
LCD1
- 用Verilog HDL编写的16*2液晶显示one world,one dream。压缩包中包括所有文件，使用的芯片为EP2C5T144，经过最后下载测试的。-Verilog HDL prepared with 16* 2 LCD display one world, one dream. Compression package, including all documents, use the chips for EP2C5T144, download final test.
FIFO
- 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
crc_32_8_fsm
- 循环校验码编码，并行编码，通过了FPGA测试验证-crc_encode, parallel coding, verified by FPGA
crc_dec
- 循环校验码解码，串行解码，通过了FPGA的测试验证-crc_dec, serial decoding, verified by FPGA
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
VHDL
- vhdl 相关知识 指令及示例 和 Physical Level Design using Synopsys-vhdl command and example of relevant knowledge and Physical Level Design using Synopsys
Modelsim_QA
- modelsim的一些问题集锦，对于从事FPGA的研发人员很有帮助-Collection of some of the problems modelsim for personnel engaged in R & D FPGA helpful
ZLG_Verilog
- 周立功verilog编程参考指南，对编程很有帮助，-Ligong weeks programming verilog reference guide for programming very useful
pa3_libguide_ug
- actel开发环境libero中应用到是一些基础宏的说明文档，很难得的资料-libero in actel application development environment are the basis of the documentation of the macro, it is difficult to get information
S5_UART
- verilog编写的UART程序，是红色飓风EP1C6板子上面的程序-this is a UART project with verilog language,it is the programmer by the redlogic s EP1C6 board