资源列表
crc_verilog_xilinx
- CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
fft_VHDL
- 使用altra的quartus8.1作为开发环境，用硬件语言VHDL实现了fft的变化-Altra as quartus8.1 use the development environment, language VHDL hardware changes to achieve the fft
uart_vhdl
- VHDL语言的实现标准的UART串口,并可以多次例化成多串口的-The realization of VHDL language standard UART serial port
pinlvji_5
- 用Verilog语言实现的5位频率计设计，为实现功能验证，测频信号是由内部时钟源分频得到，为25KHZ，数据输出为串行输出。使用的硬件资源是altera公司的EPM7218，晶振为40MHZ。-Verilog language used to achieve the five frequency meter design, to achieve functional verification, signal frequency measurement by the internal clock
VHDL
- 再FPGA上經由VGA顯示一半黑一半白的圖示-By the FPGA and then VGA display half black half white icon
fpga_lcd_vhdl
- 对于开发fpga有很好的帮助，可以快速的帮助你入门，是经典的vhdl的源程序-Fpga for the development of a very good help, you can quickly get you started, here is a classic source of vhdl
fftw3mat
- 介绍了如何利用c语言来实现数字信号处理中常用的fft，并介绍了如何利用matlab验证-intruduce how to use c to finish fft,and use matlba to ensure
alu_struct
- ALU written in VHDL, tested in FPGA advantage, there will be no support on this code. All right reserved by developer.
LCD1
- lcd controller using vhdl code
half_adder
- 一个半加器，具有进位和位数相加的基本功能，可作为全加器的基本模块-One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module